Okay.
Over the weekend I've figured out how much I can skimp on bypass capacitors, and found out one bug in PCB.
Also learned how do solder wires to 0.4mm pitch QFNs (Thank cypress for solderable QFN pin sides!)
Details:
Left one of 2 VDDD pins hanging - that's a power rail for the digital part of the chip. Of course it was the closest one to USB pins, so powering them. Caused LOTS of noise on the power rail - like 200mV drops whenever USBIO tried to drive the bus (which is CONSTANTLY).
Figured out that I skimped on bypass capacitors a bit too much and that charge bank capacitors for the ADC ext refs are good idea even when that reference is VBUS (may be "especially when", dunno
)
So, lots of very fine-pitch soldering (god bless that guy who sold 0.6mm STTC-045 with his metcal to me!) and scoping, fun weekend
Results:
1uF cap 8mm from the chip (C5 position), VDDD disconnected: noise floor 30mV, spikes up to 150mV, 20mV drops on USBIO driving impulse edge.
0.1uF cap instead: 0-150mV
0.1uF, no board connected: 0-50mV
+1uF soldered to VDDIO0 (top left on PCB): 0-15mV, 20mV drops.
+0.1uF to VDDIO0: 0-5mV, 7mV drops
VDDD resoldered to bus, 1uF @C5 only: 0-15mV, 30mV drops.
0.1@C5, 1@C6, 1@VDDIO0: 0-5mV, 4mV drops.
+board: 25-120mV, 4mV drops.
..and theeeen I discovered that I only connected chassis ground, not PCB grounds (not too long into the process, fortunately)
Final results - 15-45mV, same 4mV power drops every 1us or so due to USB.
Weakest key produces ~90mV, so there's enough SNR. Especially if you pass the readings thru IIR filter.
Also noticed that I read first column a bit early, when drive line barely reached 3V - which greatly diminished SNR. Had to code in a delay (It's actually a single-shot PWM. So delay is programmable!
) before driving the row and firing ADC sequencer.
Also various small changes
* IIR implementation with integers and no multiplication which doesn't eat precision (i.e. proper implementation),
* moved scanning to interrupts for fun and profit - scanrate is now ~5.2kHz and I can, in principle, implement noise reduction based on signal form I get (i.e. to discern between noise and incoming flipper)
* introduced rampdown delay because controller was switching on the next row too fast as a consequence of the previous. No PWM was needed there, just finding the place to get turn off signal which fires not too soon.
* made sure that _both_ ADCs complete DMA transfer before generating a "Scan complete" interrupt. Just in case.
Need this all to simmer for a day or two and then there will be a production PCB revision sent to oshpark.